1. Field of the Invention
The present invention generally relates to digital circuits for providing a delay of digital signals, and more particularly to programmable delay lines for correction, synchronization, and minimization of propagation times of digital signals.
2. Description of the Prior Art
Modern digital logic circuits such as digital logic circuits that are included in digital data processors are characterized by short signal propagation times which are enhanced by decreased switching element (e.g. transistor) sizes and increased integration density. The short signal propagation times are exploited by reducing clock cycle times so that logic functions and data processing can be carried out more rapidly. However, some signal paths will necessarily have longer propagation times than others, and intended functions cannot be carried out unless proper signals are simultaneously present. This synchronization becomes more critical as clock cycle times are reduced.
It is a common practice to provide programmable delay lines to delay selected ones of related signals to correspond to the arrival of another selected signal in order to synchronize the arrival of the plural signals at a particular node. The functional speed of an entire circuit may be determined by one or more paths through the circuit. Such a path is sometimes referred to as a critical path.
In general, it is also common practice to generate such delays in digital signals by propagating signals through a plurality of rapidly switched identical stages such as serial pairs of inverter circuits that are arrayed so propagation time over connections between stages, or between taps and an output, is substantially constant. While some variation in propagation time is inevitable, the propagation time through a pair of inverters is a sufficiently small time increment which is short compared to clock cycle time to approximate the required delay resolution.
Programmable delay elements are used in the design of delay locked loops (DLLs). In turn, a DLL may be used to delay a clock or clocks, or the transmission of data, in order to synchronize critical timings in a computer system. Sometimes, both a clock and data are delayed by a DLL to synchronize critical timings.
The ability to program such delay elements potentially reduces the design burden of designing particular delay elements for many nodes of a circuit that may correspond to a critical path. However, it should be appreciated that delay elements can consume significant amounts of chip space, depending on the maximum amount of delay to be accommodated or provided. While the maximum delay can be estimated, the maximum delay must be matched fairly closely with the actual delay needed in order to avoid excessive consumption of chip space and specific designs of delay lines for specific maximum delays may be required, depending on other design and/or operational constraints
One method of improving the timing between the elements of a chip within a computer system is the use of a digital DLL. Digital DLLs typically employ variable programmable delay lines where the incremental delay unit is one or two logic gates. However, the mere inclusion of a DLL provides some delay time that cannot be avoided. This minimum delay for which the line can be programmed is referred to as the insertion delay of a variable delay line. Thus, the insertion delay is an important property to consider in the design of a programmable variable delay line.
Insertion delay is especially important when dealing with a high frequency operation because a long insertion delay can prevent the DLL from operating at a single clock cycle. For example, if a clock is operating on a 10 ns cycle, and the latent delay associated with the clock tree is 3 ns, then a DLL will be unable to operate at a single clock cycle if the insertion delay of the DLL is greater than 7 ns. If the insertion delay of the DLL in this example was 8 ns, then the DLL would be forced to operate at a 20 ns cycle, twice the amount of a single clock cycle.
This clock cycle jump increases the vulnerability of the computer system to operational errors caused by occasional variations in the output of an associated power supply. A low insertion delay can enable the DLL to operate at a single clock cycle, thus significantly reducing or even eliminating concern regarding "jitters" or other errors caused by variations in the power supply.
Another important factor in the design of a variable delay line is the frequency range over which the line is capable of operating. A programmable delay line with a large range of delays is capable of operating over a larger frequency range than a delay line with a small range of delays. Thus, a programmable delay line with a large range of delays is superior to a delay line with a small range of delays. However, there is a trade off between chip space and resolution and maximum delay range.
It is also desirable for consistency of resolution over a range of delays to provide an equal length of delay from each tap of the delay line to the output of the multiplexer including the connections from the inverters to the multiplexer inputs. Accommodation of this preference increases the complexity of the delay line design and requires unique layouts for delay elements of each different delay to be produced. Again, there is a trade-off between chip space and the number of delay element designs which may be required in the overall logic circuit or processor design.
Another consideration in the design of programmable DLLs is the need to latch the control signals. The control signals must be stable at logic voltage levels in order to correctly control the DLL. Variance of the control voltage can affect propagation time through transmission gates in multiplexers controlling the delay path. Noise causing the control voltages to vary, even briefly, while a signal of interest is propagating through the DLL can redirect the signal, changing the delay or even allow multiple pulses to simultaneously propagate on different paths. Latches to stabilize control voltages and program the DLL before input may require a minimum of four to six elements or two to three times the footprint of a single delay element. Therefore, the footprint area of the latches can exceed the footprint area of the array of delay elements in some designs. Unfortunately, in known designs, efficiency of control signal size in number of bits of control signal is often achieved only at the expense of increased insertion delay and vice versa.